Communications of the ACM - Special issue on parallelism
ACM Computing Surveys (CSUR)
Architecture of a message-driven processor
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
iPSC/2 system: a second generation hypercube
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
System design of the J-Machine
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Design and performance of multipath MIN architectures
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
A tightly-coupled processor-network interface
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
ComPaSS: efficient communication services for scalable architectures
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
The J-machine multicomputer: an architectural evaluation
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
T: integrated building blocks for parallel computing
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Programming, compilation, and resource management issues for multithreading (panel session II)
ACM SIGARCH Computer Architecture News - Special issue: panel sessions of the 1991 workshop on multithreaded computers
Unicast-Based Multicast Communication in Wormhole-Routed Networks
IEEE Transactions on Parallel and Distributed Systems
Virtual memory mapped network interface for the SHRIMP multicomputer
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
METRO: a router architecture for high-performance, short-haul routing networks
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Tempest and typhoon: user-level shared memory
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Integration of message passing and shared memory in the Stanford FLASH multiprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
IBM Systems Journal
Evaluating the locality benefits of active messages
PPOPP '95 Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming
Optimistic active messages: a mechanism for scheduling communication with computation
PPOPP '95 Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming
Analysis and implementation of hybrid switching
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Analysis of communications and overhead reduction in multithreaded execution
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Control of loop parallelism in multithreaded code
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Adaptive Fault-Tolerant Deadlock-Free Routing in Meshes and Hypercubes
IEEE Transactions on Computers
Analysis and Implementation of Hybrid Switching
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
High-Throughput, Low-Memory Applications on the Pica Architecture
IEEE Transactions on Parallel and Distributed Systems
Models and languages for parallel computation
ACM Computing Surveys (CSUR)
25 years of the international symposia on Computer architecture (selected papers)
Virtual memory mapped network interface for the SHRIMP multicomputer
25 years of the international symposia on Computer architecture (selected papers)
Tempest and typhoon: user-level shared memory
25 years of the international symposia on Computer architecture (selected papers)
Cyclic-Cubes: A New Family of Interconnection Networks of Even Fixed-Degrees
IEEE Transactions on Parallel and Distributed Systems
Microservers: a new memory semantics for massively parallel computing
ICS '99 Proceedings of the 13th international conference on Supercomputing
IBM Systems Journal
Concurrent Event Handling through Multithreading
IEEE Transactions on Computers
Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Implementing Concurrent Object-Oriented Languages on Multicomputers
IEEE Parallel & Distributed Technology: Systems & Technology
Lee Distance and Topological Properties of k-ary n-cubes
IEEE Transactions on Computers
Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers
IEEE Transactions on Parallel and Distributed Systems
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
A Fine-Grain Threaded Abstract Machine
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Parallel Computation: MM +/- X
Informatics - 10 Years Back. 10 Years Ahead.
Gilgamesh: a multithreaded processor-in-memory architecture for petaflops computing
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
SNAP: A Sensor-Network Asynchronous Processor
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Combined DRAM and logic chip for massively parallel systems
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Design and performance evaluation of a multithreaded architecture
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Verilog modeling and simulation of a communication coprocessor for multicomputers
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
PIM Architectures to Support Petaflops Level Computation in the HTMT Machine
IWIA '99 Proceedings of the 1999 International Workshop on Innovative Architecture
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
A low cost, multithreaded processing-in-memory system
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
High Performance Computing Systems for Autonomous Spaceborne Missions
International Journal of High Performance Computing Applications
SCMP: a single-chip message-passing parallel computer
The Journal of Supercomputing - Special issue: Parallel and distributed processing and applications
Proceedings of the 34th annual international symposium on Computer architecture
Continuum: A Hybrid Time/Space Communications Paradigm for k-ary n-cubes
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
EXECUBE-A New Architecture for Scaleable MPPs
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Architectural Support for Fair Reader-Writer Locking
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Landing stencil code on Godson-T
Journal of Computer Science and Technology
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The message-driven processor (MDP), a 36-b, 1.1-million transistor, VLSI microcomputer, specialized to operate efficiently in a multicomputer, is described. The MDP chip includes a processor, a 4096-word by 36-b memory, and a network port. An on-chip memory controller with error checking and correction (ECC) permits local memory to be expanded to one million words by adding external DRAM chips. The MDP incorporates primitive mechanisms for communication, synchronization, and naming which support most proposed parallel programming models. The MDP system architecture, instruction set architecture, network architecture, implementation, and software are discussed.