Verilog modeling and simulation of a communication coprocessor for multicomputers

• Authors: A. Shyamprakash;C. P. Ravikumar
• Venue: IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
• Year: 1995

We describe the Verilog modeling and design of a static fault-tolerant hardware router for use in a communication coprocessor in distributed memory multicomputer. The coprocessor employs a wormhole routing technique for packets. Virtual channels are used to better utilize the communication bandwidth offered by the physical links. The router implements a fault-tolerant routing algorithm, which can tolerate link faults in the multicomputer. We have carried out behavioral modeling of the communication coprocessor using Verilog. We have simulated the routing in a 3-dimensional hypercube to verify the hardware design of the coprocessor.