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Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Automating Synthesis of Asynchronous Communication Mechanisms
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Buffered Asynchronous Communication Mechanisms
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
Low power programmable architecture for periodic activity monitoring
Proceedings of the ACM/IEEE 4th International Conference on Cyber-Physical Systems
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We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, the Network on a Chip (NoC), which will execute a novel sensor-network simulator. We discuss the advantages of using the same processor for nodes in physical and simulated sensor networks. We describe the attributes that a processor must possess to function well in both roles, and we then describe the way we designed SNAP to have these attributes.