Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
The Mosaic fast 512K scalable CMOS dRAM
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits
SNAP: A Sensor-Network Asynchronous Processor
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Asynchronous DRAM Design and Synthesis
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
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The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, will also require more memory than can easily be supported on logic-oriented ASIC processes. Most ASIC memory systems are P-load SRAM, but this circuit technology is neither dense nor power efficient. This paper describes development of a DRAM, compatible with a standard CMOS ASIC process, that provides memory density at least 4x improved over P-load SRAM in the same layout rules. It runs at speeds comparable to logic in the same process and uses circuitry that is reasonably simple and portable. The design employs Vdd-precharge bit lines, half-capacitance, full-voltage dummy cells, and a simple complementary sense amp. DRAM is organized as a number of small pages, allowing simple circuit design and low-power operation at modest expense in area overhead. The paper also described a power-conserving low-voltage-swing bus that intefaces multiple pages to a full-voltage-swing circuitry. Circuit and layout details are provided, along with experimental results for a 100MHz 786K-bit embedded DRAM in a 0.5 process.