Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
An O(logN) deterministic packet routing scheme
STOC '89 Proceedings of the twenty-first annual ACM symposium on Theory of computing
Practical schemes for fat-tree network construction
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Active messages: a mechanism for integrated communication and computation
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Design and performance of multipath MIN architectures
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Networks, Routers and Transputers: Function, Performance and Applications
Networks, Routers and Transputers: Function, Performance and Applications
A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor
A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor
Robust, High-Speed Network Design for Large-Scale Multiprocessing
Robust, High-Speed Network Design for Large-Scale Multiprocessing
Remote queues: exposing message queues for optimization and atomicity
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
NIFDY: a low overhead, high throughput network interface
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The Journal of Supercomputing
Minimal adaptive routing with limited injection on Toroidal k-ary n-cubes
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
A lightweight idempotent messaging protocol for faulty networks
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
MediaWorm: A QoS Capable Router Architecture for Clusters
IEEE Transactions on Parallel and Distributed Systems
Guaranteeing the quality of services in networks on chip
Networks on chip
Performance Evaluation - Special issue: Distributed systems performance
Performance Modelling and Analysis of Pipelined Circuit Switching in Hypercubes with Faults
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Communication delay analysis of fault-tolerant pipelined circuit switching in torus
Journal of Computer and System Sciences
Performance modelling of pipelined circuit switching in hypercubes with hot spot traffic
Microprocessors & Microsystems
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The Multipath Enhanced Transit Router Organization (METRO) is a flexible routing architecture for high-performance, tightly-coupled, multiprocessors and routing hubs. A METRO router is a dilated cross-bar routing component supporting half-duplex bidirectional, pipelined, circuit-switched connections. Each METRO router is self-routing and supports dynamic message traffic. The routers works in conjunction with source-responsible network interfaces to achieve reliable end-to-end data transmission in the presence of heavy network congestion and dynamic faults. METRO separates the fundamental architectural characteristics from implementation parameters. Simplicity of routing function coupled with freedom in the implementation parameters allows METRO implementations fully exploit available technology to achieve low-latency and high-bandwidth. We illustrate the effects of this implementation freedom by summarizing the performance which various METRO configurations can extract from some modern CMOS technologies. Included in our illustrations is METROJR-ORBIT, a minimal instance of the METRO architecture we constructed in a 1.2μ gate-array technology.