Communications of the ACM - Special section on computer architecture
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The iPSC/2 direct-connect communications technology
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
METRO: a router architecture for high-performance, short-haul routing networks
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Ariadne—an adaptive router for fault-tolerant multicomputers
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks
IEEE Transactions on Parallel and Distributed Systems
A Performance Model for Duato's Fully Adaptive Routing Algorithm in k$k$-Ary n$n$-Cubes
IEEE Transactions on Computers
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Comparative Study of Switching Methods in Multicomputer Networks
The Journal of Supercomputing
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Modeling of Pipelined Circuit Switching in Multicomputer Networks
MASCOTS '00 Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Analytical modelling of networks in multicomputer systems under bursty and batch arrival traffic
The Journal of Supercomputing
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Large-scale parallel systems, Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and cluster computers are often composed of hundreds or thousands of components (such as routers, channels and connectors) that collectively possess failure rates higher than what arise in the ordinary systems. One of the most important issues in the design of such systems is the development of the efficient fault-tolerant mechanisms that provide high throughput and low latency in communications to ensure that these systems will keep running in a degraded mode until the faulty components are repaired. Pipelined Circuit Switching (PCS) has been suggested as an efficient switching method for supporting inter-processor communications in networks due to its ability to preserve both communication performance and fault-tolerant demands in such systems. This paper presents a new mathematical model to investigate the effects of failures and capture the mean message latency in torus using PCS in the presence of faulty components. Simulation experiments confirm that the analytical model exhibits a good degree of accuracy under different working conditions.