Performance Modelling and Analysis of Pipelined Circuit Switching in Hypercubes with Faults

  • Authors:

  • F. Safaei;A. Khonsari;M. Fathy;M. Ould-Khaoua

  • Affiliations:

  • Institute for Studies in Theoretical Physics and Mathematics (IPM), Iran;Dept. of Electrical and Computer Engineering University of Tehran, Iran.;Dept. of Ccomputer Engineering, Iran Univ. of Science and Technology, Iran.;Dept. of Computing Science, University of Glasgow, UK.

  • Venue:
  • HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
  • Year:
  • 2005

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Abstract

Multicomputer systems are more susceptible to failure than conventional uniprocessor machines. This is because as the system size scales up, the probability of a component failure also increases. It is therefore essential to use fault-tolerant routing that allows messages to reach their destinations even in the presence of faults. Pipelined Circuit Switching (PCS) that has been employed as an efficient switching method in the design of fault-tolerant routing algorithm for reliable interprocessor networks can route a message from source to destination, even in the presence of faulty components. The analytical model of PCS for common networks (e.g., hypercube) in the absence of faulty components has recently been reported in the literature. However, none of these analytical models attempt to capture the effects of faulty nodes or links in the performance of the networks. This paper proposes a new analytical model of PCS, in the presence of faulty nodes, in the hypercube networks augmented with virtual channels. The model makes latency predictions that are in good agreement with those obtained from simulation experiments.