Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
A framework for adaptive routing in multicomputer networks
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Mayfly: a general-purpose, scalable, parallel processing architecture
Lisp and Symbolic Computation
A programmable routing controller supporting multi-mode routing and switching in distributed real-time systems
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
IEEE Transactions on Parallel and Distributed Systems
A programmable routing controller for flexible communications in point-to-point networks
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Architecture and Implementation of Vulcan
Proceedings of the 8th International Symposium on Parallel Processing
The chaos router chip: design and implementation of an adaptive router
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
PP-MEss-SIM: a simulator for evaluating multicomputer interconnection networks
SS '95 Proceedings of the 28th Annual Simulation Symposium
A Router Architecture for Flexible Routing and Switching in Multihop Point-To-Point Networks
IEEE Transactions on Parallel and Distributed Systems
Hardware for multiconnected networks: a case study
Information Sciences—Informatics and Computer Science: An International Journal - Special issue: Informatics and computer science intelligent systems applications
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
On Bandwidth Adjusted Multicast Communications in Pipeline Router Architecture
The Journal of Supercomputing
Layered switching for networks on chip
Proceedings of the 44th annual Design Automation Conference
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
On bandwidth adjusted multicast in pipelined routing architecture for mobile environment
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartII
Microprocessors & Microsystems
Proceedings of the 13th International Conference on Computer Systems and Technologies
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The switching scheme of a point-to-point network determines how packets flow through each node, and is a primary element in determining the network's performance. In this paper, we present and evaluate a new switching scheme called hybrid switching. Hybrid switching dynamically combines both virtual cut-through and wormhole switching to provide higher achievable throughput than wormhole alone, while significantly reducing the buffer space required at intermediate nodes when compared to virtual cut-through. This scheme is motivated by a comparison of virtual cut-through and wormhole switching through cycle-level simulations, and then evaluated using the same methods. To show the feasibility of hybrid switching, as well as to provide a common base for simulating and implementing a variety of routing and switching schemes, we have designed SPIDER, a communication adapter built around a custom ASIC called the Programmable Routing Controller (PRC).