Implications of structured programming for machine architecture
Communications of the ACM
Communications of the ACM
Ethernet: distributed packet switching for local computer networks
Communications of the ACM
The Smalltalk-76 programming system design and implementation
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A processor for a high-performance personal computer
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Cache memories for PDP-11 family computers
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Experience with a microprogrammed Interlisp system
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Performance of the GE-645 associative memory while Multics is in operation
Proceedings of the SIGOPS workshop on System performance evaluation
TEX and METAFONT: New directions in typesetting
TEX and METAFONT: New directions in typesetting
Computer
An Investigation of Alternative Cache Organizations
IEEE Transactions on Computers
Slave Memories and Segmentation
IEEE Transactions on Computers
The Lincoln TX-2 input-output system
IRE-AIEE-ACM '57 (Western) Papers presented at the February 26-28, 1957, western joint computer conference: Techniques for reliability
An efficient algorithm for exploiting multiple arithmetic units
IBM Journal of Research and Development
Structural aspects of the system/360 model 85: II the cache
IBM Systems Journal
| Hi-index | 14.98 |
The memory system of the Dorado, a compact high- performance personal computer, has very high I/O bandwidth, a large paged virtual memory, a cache, and heavily pipelined control; this paper discusses all of these in detail. Relatively low-speed I/O devices transfer single words to or from the cache; fast devices, such as a color video display, transfer directly to or from main storage while the processor uses the cache. Virtual addresses are used in the cache and for all I/O transfers. The memory is controlled by a seven-stage pipeline, which can deliver a peak main-storage bandwidth of 533 million bits/s to service fast I/O devices and cache misses. Interesting problems of synchronization and scheduling in this pipeline are discussed. The paper concludes with some performance measurements that show, among other things, that the cache hit rate is over 99 percent.