Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
IEEE Transactions on Computers
A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Efficient and realistic simulation of disk cache performance
ANSS '88 Proceedings of the 21st annual symposium on Simulation
Inexpensive implementations of set-associativity
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
A low-overhead coherence solution for multiprocessors with private cache memories
25 years of the international symposia on Computer architecture (selected papers)
ACM Computing Surveys (CSUR)
Transient behavior of cache memories
ACM Transactions on Computer Systems (TOCS)
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
On the BLI-model of program behaviour
SIGMETRICS '83 Proceedings of the 1983 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Effects of cache coherency in multiprocessors
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Analysis of multiprocessor cache organizations with alternative main memory update policies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Design considerations for the VLSI processor of X-TREE
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Levels of representation of programs and the architecture of universal host machines
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Performance of cache-based multiprocessors
SIGMETRICS '81 Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Performance evaluation and prediction of storage hierarchies
PERFORMANCE '80 Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation
Experimental evaluation of on-chip microprocessor cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cache hit ratios with geometric task switch intervals
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
High-speed buffering for variable length operands
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Cache memory for microprocessors
ACM SIGARCH Computer Architecture News
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Modular Minicomputers Using Microprocessors
IEEE Transactions on Computers
Design Considerations for Single-Chip Computers of the Future
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Some Performance Issues in Multiprocessor System Design
IEEE Transactions on Computers
A Recovery Cache for the PDP-11
IEEE Transactions on Computers
The Memory System of a High-Performance Personal Computer
IEEE Transactions on Computers
Effects of Cache Coherency in Multiprocessors
IEEE Transactions on Computers
Synapse tightly coupled multiprocessors: a new approach to solve old problems
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
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This paper gives a summary of the research which led to the design of the cache memory in the DEC PDP-11/70. The concept of cache memory is introduced together with its major organizational parameters: size, associativity, block size, replacement algorithm, and write strategy. Simulation results are given showing how the performance of the cache varies with changes in these parameters. Based on these simulation results the design of the 11/70 cache is justified.