An experiment in high level language microprogramming and verification
Communications of the ACM
Dynamic microprogramming: processor organization and programming
Communications of the ACM
A microprogrammed implementation of EULER on IBM system/360 model 30
Communications of the ACM
ALGOL Sixty Compilation and Assessment
ALGOL Sixty Compilation and Assessment
Introduction to VLSI Systems
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Data structure architectures - a major operational principle
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Cache memories for PDP-11 family computers
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Communication In X-TREE, A Modular Multiprocessor System
ACM '78 Proceedings of the 1978 annual conference
Microprogrammed implementation of a single chip microprocessor
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Towards a discipline of real-time programming
Proceedings of an ACM conference on Language design for reliable software
The structure of directly executed languages: a new theory of interpretive system design
The structure of directly executed languages: a new theory of interpretive system design
Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
RISC I: a reduced instruction set VLSI computer
25 years of the international symposia on Computer architecture (selected papers)
High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
XOS: an operating system for the X-tree architecture
ACM SIGOPS Operating Systems Review
Design Considerations for Single-Chip Computers of the Future
IEEE Transactions on Computers
Embedding Tree Structures in VLSI Hexagonal Arrays
IEEE Transactions on Computers
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X-NODE is a single-chip VLSI processor to be realized in the mid 1980's and to be used as a building block for a tree-structured multiprocessor system (X-TREE). Three major trends influence the design of this processor: the continuing evolution of VLSI technology, the requirements for parallelism and communication in a multiprocessor system, and the need for better support of software and high level language constructs. The influence of these trends on the processor architecture are discussed and the current state of the design of X-NODE is outlined. X-NODE will introduce several new features exploiting the full potential of VLSI technology. The processor and hierarchical memory of multiple device types will be combined on a single chip to provide a powerful processor. With basically a memory-to-memory architecture, an on-chip caching scheme provides the performance of a register based architecture. This on-chip memory hierarchy contains program and data, as well as microcode. The instruction set of any processor can thus be dynamically changed and tailored to the specific problem being executed. It is planned to support high level language constructs directly in hardware through mechanisms such as bounds checking.