Technical aspects of data communication (3rd ed.)
Technical aspects of data communication (3rd ed.)
A general purpose array with a broad spectrum of applications
Computer Architecture, Workshop of the Gesellschaft für Informatik
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A hierarchical, restructurable multi-microprocessor architecture
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Competitive fault-tolerance in area-universal networks
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay
IEEE Transactions on Computers
Response Time Analysis of Multiprocessor Computers for Database Support
ACM Transactions on Database Systems (TODS)
The effect of VLSI on computer architecture
ACM SIGARCH Computer Architecture News
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
A neighbor connected processor network for performing relational algebra operations
CAW '80 Proceedings of the fifth workshop on Computer architecture for non-numeric processing
The Apiary network architecture for knowledgeable systems
LFP '80 Proceedings of the 1980 ACM conference on LISP and functional programming
Design considerations for the VLSI processor of X-TREE
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
XOS: an operating system for the X-tree architecture
ACM SIGOPS Operating Systems Review
Design Considerations for Single-Chip Computers of the Future
IEEE Transactions on Computers
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A communication network for a tree-structured assembly (X-TREE) of single-chip processors is described, and considerations for selecting this particular approach are discussed. The communication links between the processors are high-speed, byte-parallel connections with an asynchronous handshaking protocol. Each node of X-TREE consists of a powerful processor, a switching network and a dedicated communications controller. The latter checks the availability of the links terminating in this node, supervises the creation and elimination of message channels and controls the routing and time multiplexing of concurrent messages over the same link. The switching network inside each X-NODE connects the external links with the internal processor via a fast multiplexed bus which is interfaced to each input/output port through fifo message buffers. Network topology, routing algorithm, addressing scheme, message format and communication hardware are discussed.