Communications of the ACM - Special issue on computer architecture
A microprogrammed implementation of EULER on IBM system/360 model 30
Communications of the ACM
Introduction to VLSI Systems
Design considerations for the VLSI processor of X-TREE
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Cache memories for PDP-11 family computers
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Communication In X-TREE, A Modular Multiprocessor System
ACM '78 Proceedings of the 1978 annual conference
Microprogrammed implementation of a single chip microprocessor
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Am2900 Bipolar Microprocessor family
MICRO 8 Proceedings of the 8th annual workshop on Microprogramming
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
Architecture of a New Microprocessor
Computer
Heuristic Synthesis of Microprogrammed Computer Architecture
IEEE Transactions on Computers
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Comments on "A Massive Memory Machine"
IEEE Transactions on Computers
A state-of-the-art SIMD two-dimensional FFT array processor
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
On the design of Always Compatible Instruction Set Architecture(ACISA)
ACM SIGARCH Computer Architecture News
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
The architecture of MANIP: a parallel computer system for solving NP-complete problems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
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In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one milion transistors to the various functional blocks is given, and the result is a memory intensive design.