Modular Minicomputers Using Microprocessors

Authors:
J. A. Arulpragasam;R. A. Giggi;R. F. Lary;D. T. Sullivan; Chin-Chang Wu
Affiliations:
Digital Equipment Corporation;-;-;-;-
Venue:
IEEE Transactions on Computers
Year:
1980

Citing 4
Cited 1

Multiprocessor Organization—a Survey

ACM Computing Surveys (CSUR)
Cache memories for PDP-11 family computers

ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Cm*: a modular, multi-microprocessor

AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Distributed data processing

IBM Systems Journal

Poolpo A Pool of Processors for Process Control Applications

IEEE Transactions on Computers

Quantified Score

Hi-index	14.98

Visualization

Abstract

This paper presents the design and breadboard implementation of an experimental multiprocessor (mP) whose objectives were 1) to provide modularity of performance over the range of 0.2 million instructions/s (mips) to about 3 mips and 2) to optimize cost-performance over this selected range by exploiting the high technology of microprocessors and RAM's.