Planning a computer system: Project Stretch
Planning a computer system: Project Stretch
Reducing Cache Conflicts by a Parametrized Memory Mapping
ParNum '99 Proceedings of the 4th International ACPC Conference Including Special Tracks on Parallel Numerics and Parallel Computing in Image Processing, Video Processing, and Multimedia: Parallel Computation
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
Multiple Microprocessors with Common Main and Control Memories
IEEE Transactions on Computers
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers
On the Bandwidth and Interference in Interleaved Memory Systems
IEEE Transactions on Computers
Organization of semiconductor memories for parallel-pipelined processors
IEEE Transactions on Computers - Special issue on parallel processors and processing
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There is frequently a severe mismatch between achievable processor and memory speeds in today's computer systems. For example, the CDC-7600 has a 27ns (nanosecond) processor cycle time and a 270ns memory cycle time; the IBM-360/91 has a 60ns processor cycle time and a 750 ns memory cycle time. In order to obtain the desired increase in the effective memory speed, an efficient memory system must use such techniques as interleaving memory modules and implementing an automatic level in a memory hierarchy (e.g., a slave memory as in the IBM-360/85 or 195 and the CDC-7600). In the past, interleaving was often studied by simulation using a random address generating source to obtain memory requests. This paper discusses results of mathematical analyses of models of interleaved memory systems. In these investigations the properties of addresses generated by instructions and data have been distinguished.