Optimal Searching Algorihtms for Parallel Pipelined Computers
Proceedings of the Sagamore Computer Conference on Parallel Processing
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers
A study of interleaved memory systems
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
On the Bandwidth and Interference in Interleaved Memory Systems
IEEE Transactions on Computers
A performance study of buffered pseudorandomly interleaved memories with multiple sections
Mathematical and Computer Modelling: An International Journal
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An organization of interleaved multimodule semiconductor memories is studied to facilitate accessing of memory words by a parallel-pipelined processor. All modules are assumed to be identical and to have address cycle (address hold time) and memory cycle of a and c segment time units, respectively. A total of N(=2n) memory modules are arranged such that there are l(=2b) lines for addresses and m(=2n-b) memory modules per line. For a parallel-pipelined processor of order (s,p) which consists of p parallel processors each of which has s degrees of multiprogramming, there can be up to s ċ p memory requests in each instruction cycle. Memory request collisions are bound to occur in such a system. Performance is evaluated as a function of the memory configuration. Results show that for reasonably large values of N, high performance caD. be obtained even in the nonbuffered case when l is a ċ p or more. Buffering has maximum effect on performance when l is near a ċ p. When l must be greater than a ċ p for adequate performance in the nonbuffered case, buffering can be used to reduce l while maintaining performance.