Coupling small computers for performance enhancement

  • Authors:
  • Fernando C. Colon;Robert M. Glorioso;Walter H. Kohler;Dominic W. Li

  • Affiliations:
  • University of Massachusetts, Amherst, Massachusetts;University of Massachusetts, Amherst, Massachusetts;University of Massachusetts, Amherst, Massachusetts;University of Massachusetts, Amherst, Massachusetts

  • Venue:
  • AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
  • Year:
  • 1976

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Abstract

The advent of the microprocessor has opened up new avenues for the system designer to provide more powerful, more reliable and more user oriented computer systems to the user community for the same or lower costs. The problem confronting the designer is: How to achieve these goals? This paper describes one such method called Distributed Function Multiple Processor (DFMP). The system described uses several micro processors each with its own memory to form a cluster. These processors are differentiated by the functions they perform such as file managing, intelligent terminal, etc. and communicate via a Restricted Cross Bar Switch (RCBS). Further, several clusters or nodes can be linked to form a local network. Interprocessor and internode communications are controlled by a special processor called the Interprocessor Controller (PC) located in each node. The IPC's use an adaptive technique to determine traffic flows.