Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The architecture of microprocessors
The architecture of microprocessors
Implementing mathematics with the Nuprl proof development system
Implementing mathematics with the Nuprl proof development system
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An introduction to mathematical logic and type theory: to truth through proof
An introduction to mathematical logic and type theory: to truth through proof
Experiences in commercial VLSI microprocessor design
Microprocessors & Microsystems
The notion of proof in hardware verification
Journal of Automated Reasoning
Computer architecture and design
Computer architecture and design
Microprocessor design verification
Journal of Automated Reasoning
High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
Specification-driven design of custom hardware in HOP
Current trends in hardware verification and automated theorem proving
Formal verification of a microprocessor using equational techniques
Current trends in hardware verification and automated theorem proving
ML for the working programmer
Branch Strategies: Modeling and Optimization (Pipeline Processing)
IEEE Transactions on Computers
The SECD microprocessor: a verification case study
The SECD microprocessor: a verification case study
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
The industrial use of formal methods
Microprocessors & Microsystems - Special issue on safety-critical systems
Synthesis of pipelined instruction set processors
DAC '93 Proceedings of the 30th international Design Automation Conference
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Structuring and automating hardware proofs in a higher-order theorem-proving environment
Formal Methods in System Design - Special issue on computer-aided verification: special methods II
Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal verification of pipeline conflicts in RISC processors
EURO-DAC '94 Proceedings of the conference on European design automation
Formal Modeling and Verification of Microprocessors
IEEE Transactions on Computers
Formal Methods in System Design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
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VLSI RISC Architecture and Organization
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High-Level Language Computer Architecture
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Formal Verification of a Pipelined Microprocessor
IEEE Software
Efficient Instruction Sequencing with Inline Target Insertion
IEEE Transactions on Computers
Reasoning About Pipelines with Structural Hazards
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Mechanically Checking a Lemma Used in an Automatic Verification Tool
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Modelling Bit Vectors in HOL: the word library
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
Implementing a Methodology for Formally Verifying RISC Processors in HOL
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL
Proceedings of the 7th International Workshop on Higher Order Logic Theorem Proving and Its Applications
Embedding Hardware Verification Within a Commercial Design Framework
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Using Transformations and Verification in Ciruit Design
Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A Correctness Model for Pipelined Multiprocessors
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
High-confidence design for security: don't trust—verify
Communications of the ACM
Modelling and verification of superscalar Micro-architectures functional approach
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
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In this paper a practical methodology for formally verifyingRISC cores is presented. Using a hierarchical model which reflectsthe abstraction levels used by designers of real RISC processors,proofs between neighboring levels are performed for simplifying theverification process. The proofs are performed by showing that eachinstruction is executed correctly by the pipelined machine withrespect to the semantics of the instruction set architecture. Duringthis proof, temporal abstractions are used to find correspondencesbetween the various levels of abstractions. Additionally, lowerlevel implementational details such as, multiphased clocks and gatelevel descriptions of the final implementation, are accounted for.The overall correctness proof is managed in two complementary steps,namely, {\it pipeline\ data} and {\it pipeline\ control} correctness.In the former, we show that the cumulative effect of pipelinesuboperations yields the data semantics of architecture instructions.While in the latter, we are concerned with interferences (conflicts)between the different instructions and suboperations in the pipeline.We have developed a set of parametrized proof scripts which highlyautomate the different proof tasks. In addition, the pipeline controlproof is constructive, in the sense that the conditions under whichthe pipeline conflicts occur are automatically generated andexplicitly stated thus aiding the user in its removal. All developedspecifications and proof scripts are kept general, so that themethodology could be applied for a wide range of RISC cores (e.g.,those used in embedded systems). In this paper, the describedformalization and proof strategies are illustrated via the DLX RISCprocessor.