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CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
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The trend in microprocessor design is to extend instruction-set architectures with features--such as parallelism annotations, predication, speculative memory access, or multimedia instructions--that allow the compiler or programmer to express more instruction-level parallelism than the microarchitecture is willing to derive. In this paper we show how these instruction-set extensions can be put to use when formally verifying the correctness of a microarchitectural model. Inspired by Intel's IA-64, we develop an explicitly parallel instruction-set architecture and a clustered microarchitectural model. We then describe how to formally verify that the model implements the instruction set. The contribution of this paper is a specification and verification method that facilitates the decomposition of microarchitectural correctness proofs using instruction-set extensions.