Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Simplification by Cooperating Decision Procedures
ACM Transactions on Programming Languages and Systems (TOPLAS)
REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs
REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Proceedings of the 42nd annual Design Automation Conference
Application of Formal Word-Level Analysis to Constrained Random Simulation
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
The heuristic theorem prover: yet another SMT modulo theorem prover
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
An incremental and layered procedure for the satisfiability of linear arithmetic logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Lemma learning in SMT on linear constraints
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Efficient state space exploration: interleaving stateless and state-based model checking
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
This paper describes how term-if-then-else (term-ITE ) is handled in Satisfiability Modulo Theories (SMT) and to decide Linear Arithmetic Logic (LA ) in particular. Term-ITEs allow one to conveniently express verification conditions; hence, they are very common in practice. However, the theory provers of SMT solvers are usually designed to work on conjunctions of literals; therefore, the input formulae are rewritten so as to eliminate term-ITEs. The challenge in rewriting is to avoid introducing too many new variables, while avoiding as often as possible the exponential explosion that is frequent when a naive approach is applied. We propose a solution that is based on cofactoring and theory propagation, which often produces orders-of-magnitude speedups in several SMT solvers for LA problems.