Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Accelerating switch-level simulation by function caching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic minimization using two-column rectangle replacement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient Term-ITE Conversion for Satisfiability Modulo Theories
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Manipulating MAXLIVE for spill-free register allocation
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
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This article describes the use of binary decision diagrams (BDDs) and if-then-else DAGs for representing and manipulating Boolean functions. Two-cuts are defined for binary decision diagrams, and the relationship is exhibited between general if-then-else expressions and the two-cuts of a BDD for the same function. An algorithm for computing all two-cuts of a BDD in O(n2) time is given. A new canonical form for if-then-else DAGs, analogous to Bryant''s canonical form for BDDs, is introduced. The canonical form is based on representing the lowest non-trivial two-cut in the corresponding BDD, while Bryant''s canonical form represents the highest two-cut. Expressions in Bryant''s canonical form or in the new canonical form are shown to be prime and irredundant. Some applications of if-then-else DAGs to multi-level logic minimization are given, and the Printform transformations for reducing the complexity of if-then-else DAGs are presented.