Logical Relations in Circuit Verification

  • Authors:
  • Mia Indrika

  • Affiliations:
  • -

  • Venue:
  • ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
  • Year:
  • 1999

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Abstract

We present a verification methodology for combinational arithmetic circuits which allows us to reason about circuits at a high level of abstraction and to have better-structured and compositional proofs. This is obtained using a categorical characterisation of the notion of data refinement. Within this categorical framework we introduce a notion of logical relation to deal with a language for hardware description.