ATM switch design by high-level modeling, formal verification and high-level synthesi

Authors:
S. P. Rajan;M. Fujita;K. Yuan;M. T-C. Lee
Affiliations:
Fujitsu Lab. of America, Sunnyvale, CA;Fujitsu Lab. of America, Sunnyvale, CA;Fujitsu Lab. of America, Sunnyvale, CA;Avant! Corporation, Freemont, CA
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
1998

Citing 4
Cited 1

Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

DAC '96 Proceedings of the 33rd annual Design Automation Conference
An Integration of Model Checking with Automated Proof Checking

Proceedings of the 7th International Conference on Computer Aided Verification
PVS: Combining Specification, Proof Checking, and Model Checking

CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs

GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI

PVS: An Experience Report

FM-Trends 98 Proceedings of the International Workshop on Current Trends in Applied Formal Method: Applied Formal Methods

Quantified Score

Hi-index	0.00

Visualization

Abstract

Asynchronous Transfer Mode (ATM) has emerged as a backbone for high-speed broadband telecommunication networks. In this paper, we present ATM switch design, starting from a parametric high-level model and debugging the model using a combination of formal verification and simulation. The model has been used to synthesize ATM switches according to customers' choices, by choosing concrete values for each of the generic parameters. We provide a pragmatic combination of simulation, model checking, and theorem proving to gain confidence in the ATM switch design correctness.