Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Toward compiler implementation correctness proofs
ACM Transactions on Programming Languages and Systems (TOPLAS)
ML for the working programmer
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Higher order logic and hardware verification
Higher order logic and hardware verification
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Formal Verification of a Partial-Order Reduction Technique for Model Checking
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Importing MDG Verification Results into HOL
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Reachability Programming in HOL98 Using BDDs
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Hierarchical Verification Using an MDG-HOL Hybrid Tool
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
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We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using a simplified version of the MDG system and the HOL system. Firstly, we have verified aspects of correctness of a simplified version of the MDG system. We have made certain that the semantics of a program is preserved in those of its translated form. Secondly, we have provided a formal linkage between the MDG system and the HOL system based on importing theorems. The MDG verification results can be formally imported into HOL to form a HOL theorem. Thirdly, we have combined the translator correctness theorems and importing theorems. This allows the MDG verification results to be imported in terms of a high level language (MDG-HDL) rather than a low level language. We also summarize a general method to prove existential theorems for the design. The feasibility of this approach is demonstrated in a case study that integrates two applications: hardware verification (in MDG) and usability verification (in HOL). A single HOL theorem is proved that integrates the two results.