Verifying properties of large sets of processes with network invariants
Proceedings of the international workshop on Automatic verification methods for finite state systems
Design and validation of computer protocols
Design and validation of computer protocols
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
ACM Transactions on Programming Languages and Systems (TOPLAS)
Ready-Simulation Is Not Ready to Express a Modular Refinement Relation
FASE '00 Proceedings of the Third Internationsl Conference on Fundamental Approaches to Software Engineering: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Introducing Dynamic Constraints in B
B '98 Proceedings of the Second International B Conference on Recent Advances in the Development and Use of the B Method
Proceedings of the 7th International Conference on Computer Aided Verification
Modular Verification of Dynamic Properties for Reactive Systems
IFM '99 Proceedings of the 1st International Conference on Integrated Formal Methods
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Synchronized Parallel Composition of Event Systems in B
ZB '02 Proceedings of the 2nd International Conference of B and Z Users on Formal Specification and Development in Z and B
Reformulation: A Way to Combine Dynamic Properties and B Refinement
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
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We propose a way to introduce dynamic properties into a B refinement design which differs from the approach used by J.R. Abrial and L. Mussat. First, the properties are expressed in the Propositional Linear Temporal Logic PLTL. Second, the user directs the evolution of properties through the refinement, so that a property P expressed by a formula F1 in the abstract system, is expressed again by a formula F2 in the refined system. Third, the verification combines proof and model-checking. In particular, F1 is model-checked, and, then, to ensure F2 it suffices to prove some propositions depending on the shapes of F1 and F2. In this paper, we show how to obtain these "sufficient propositions" from a refinement relation and the semantics of PLTL formulae. The main advantage is that the user does not need a variant or a loop invariant to achieve an automatic proof for finite state event systems. Our approach is illustrated on a protocol between a chip card and a card reader, called protocol T=1.