Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Handbook of theoretical computer science (vol. B)
Handbook of theoretical computer science (vol. B)
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Tearing based automatic abstraction for CTL model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Modalities for model checking (extended abstract): branching time strikes back
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
Handbook of Theoretical Computer Science
Handbook of Theoretical Computer Science
Introduction to VLSI Systems
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
IEEE Transactions on Computers
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A formal verifier is an automated decision procedure that can prove or disprove a set of statements in some logical system of reasoning. Problems informal verification have been posed and studied in a variety of disciplines for many years. However the last ten years have produced significant advances in both the theory and practical art of building formal verifiers. Various formal proof techniques available today include language containment, model checking, equivalence checking, symbolic simulation and theorem proving. In this tutorial, we will be restricting ourselves to the formal finite state machine based techniques: language containment, model checking and equivalence checking. A brief introduction to the technologies that underly these techniques will be presented as well. The tutorial will conclude with some examples of how formal methods can be employed in the verification of hardware systems.