Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Robust latch mapping for combinational equivalence checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An ATPG-Based Framework for Verifying Sequential Equivalence
Proceedings of the IEEE International Test Conference on Test and Design Validity
Solving the latch mapping problem in an industrial setting
Proceedings of the 40th annual Design Automation Conference
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
Efficient equivalence checking with partitions and hierarchical cut-points
Proceedings of the 41st annual Design Automation Conference
Timing optimization by replacing flip-flops to latches
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Processor Description Languages
Processor Description Languages
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
| Hi-index | 0.00 |
An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified. Both non-function and function-based matching methods are usually employed in commercial verification tools. In this paper, we describe a heuristic algorithm using ATPG for matching compare-points based on the functionality of the combinational blocks in the sequential designs. Results on industrial-sized circuits show our methods are both practical and efficient.