An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Robust latch mapping for combinational equivalence checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
An efficient filter-based approach for combinational verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Computers
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Previous results show that both flat and hierarchical methodologies present obstacles to effectively completing combinational equivalence checking. A new approach that combines the benefits while effectively dealing with the pitfalls of both styles of equivalence checking is presented.