An ATPG-Based Framework for Verifying Sequential Equivalence

Record & play: a structural fixed point iteration for sequential circuit verification

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Analysis of composition complexity and how to obtain smaller canonical graphs

Proceedings of the 37th Annual Design Automation Conference

AQUILA: An Equivalence Checking System for Large Sequential Designs

IEEE Transactions on Computers

A practical and efficient method for compare-point matching

Proceedings of the 39th annual Design Automation Conference

Using ATPG for clock rules checking in complex scan designs

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop