Automating recursive type definitions in higher order logic
Current trends in hardware verification and automated theorem proving
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Higher order logic and hardware verification
Higher order logic and hardware verification
Communicating sequential processes
Communications of the ACM - Special 25th Anniversary Issue
Experience with Embedding Hardware Description Languages in HOL
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
On the Axiomatic Treatment of Concurrency
Seminar on Concurrency, Carnegie-Mellon University
prialt in Handel-C: an operational semantics
International Journal on Software Tools for Technology Transfer (STTT) - Special section on formal methods for industrial critical systems
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
Mechanised Wire-wise Verification of Handel-C Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
UTP'08 Proceedings of the 2nd international conference on Unifying theories of programming
Mechanised wire-wise verification of Handel-C synthesis
Science of Computer Programming
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Handel-C is a hybrid language based on C and CSP for the high level description of hardware components. Several semantic models for the language and a non-rigorous compilation mechanism have been proposed for it. The compilation has been empirically validated and used in commercial tools, but never formally verified. This work presents a semantic model of the generated hardware and establishes the foundations for the formal verification of correctness of the transformation approach.