Mechanised Wire-wise Verification of Handel-C Synthesis

Authors:
Juan Ignacio Perna;Jim Woodcock
Affiliations:
Computer Science Department, The University of York, York, United Kingdom;Computer Science Department, The University of York, York, United Kingdom
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2009

Citing 3
Cited 1

Communicating sequential processes

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A denotational semantics for Handel-C hardware compilation

ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
A denotational semantics for Handel-C

Formal methods and hybrid real-time systems

Mechanised wire-wise verification of Handel-C synthesis

Science of Computer Programming

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Abstract

The compilation of Handel-C programs into net-list descriptions of hardware components has been extensively used in commercial tools but never formally verified. In this paper, we first introduce a variation of the existing semantic model for Handel-C compilation that is amenable for mechanical proofs and detailed enough to analyse properties about the generated hardware. We use this model to prove the correctness of the wiring schema used to interconnect the components at the hardware level and propagate control signals among them. Finally, we present the most interesting aspects of the mechanisation of the model and the correctness proofs in the HOL theorem prover.