Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Automatic formal verification of DSP software
Proceedings of the 37th Annual Design Automation Conference
Translation validation for an optimizing compiler
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Automatic formal verification for scheduled VLIW code
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Automated Software Engineering
A formal verification technique for embedded software
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Symbolic Simulation Techniques - State-of-the-art and Applications
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An equivalence checking methodology for hardware oriented C-based specifications
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Automatic functional verification of memory oriented global source code transformations
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Embedded software verification using symbolic execution and uninterpreted functions
International Journal of Parallel Programming
Proceedings of the 43rd annual Design Automation Conference
Finding and understanding bugs in C compilers
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Detecting inconsistencies in wrappers: a case study
Proceedings of the 2013 International Conference on Software Engineering
Data-driven equivalence checking
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
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Like hardware, embedded software faces stringent design constraints, undergoes extremely aggressive optimization, and therefore has a similar need for verifying the functional equivalence of two versions of a design, e.g., before and after an optimization. The concept of cutpoints was a breakthrough in the formal equivalence verification of combinational circuits and is the key enabling technology behind its successful commercialization. We introduce an analogous idea for formally verifying the equivalence of structurally similar, "combinational" software, i.e., software routines that compute a result and return/terminate, rather than executing indefinitely. We have implemented a proof-of-concept cutpoint approach in our prototype verification tool for the TI C6x family of VLIW DSPs, and our experiments show large improvements in runtime and memory usage.