Automatic formal verification for scheduled VLIW code

Authors:
Xiushan Feng;Alan J. Hu
Affiliations:
University of British Columbia;University of British Columbia
Venue:
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Year:
2002

Citing 7
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Abstract

VLIW processors are attractive for many embedded applications, but VLIW code scheduling, whether by hand or by compiler, is extremely challenging. In this paper, we extend previous work on automated verification of low-level software to handle the complexity of modern, aggressive VLIW designs, e.g., the exposed parallelism, pipelining, and resource constraints. We implement these ideas into a prototype tool for verifying short sequences of assembly code for TI's C62x family of VLIW DSPs, and demonstrate the effectiveness of the tool in quickly verifying, or finding bugs in, two difficult-to-analyze code segments.