Formal verification with Isabelle/HOL in practice: finding a bug in the GCC scheduler

Authors:
Lars Gesellensetter;Sabine Glesner;Elke Salecker
Affiliations:
Institute for Software Engineering and Theoretical Computer Science, Technical University of Berlin, Berlin, Germany;Institute for Software Engineering and Theoretical Computer Science, Technical University of Berlin, Berlin, Germany;Institute for Software Engineering and Theoretical Computer Science, Technical University of Berlin, Berlin, Germany
Venue:
FMICS'07 Proceedings of the 12th international conference on Formal methods for industrial critical systems
Year:
2007

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Abstract

Software bugs can cause tremendous financial loss and are aserious threat to life or physical condition in safety-critical areas. Formalsoftware verification with theorem provers aims at ensuring that no errorsare present but is too expensive to be employed for full-scale systems.We show that these costs can be reduced significantly by reusing proofsand by the checker approach. We demonstrate the applicability of ourapproach by a case study checking the correctness of the scheduler of thepopular GCC compiler for a VLIW processor where we indeed found anerror.