Symbolic Simulation Heuristics for High-Level Design Descriptions with Uninterpreted Functions

Authors:
Kiyoharu Hamaguchi
Affiliations:
-
Venue:
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Year:
2001

Citing 0
Cited 2

Automatic formal verification for scheduled VLIW code

Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Embedded software verification using symbolic execution and uninterpreted functions

International Journal of Parallel Programming

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Abstract

This paper handles symbolic simulation for high-level design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named ``symbolic function table'' and ``synchronization''. In the experiment, the equivalence of a hardware/software codesign was checed up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our prototype symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics, up to tens of thousands of cycles.