Automatic formal verification for scheduled VLIW code
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Cutpoints for formal equivalence verification of embedded software
Proceedings of the 5th ACM international conference on Embedded software
Embedded software verification using symbolic execution and uninterpreted functions
International Journal of Parallel Programming
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A number of different techniques of symbolic simulation in particular at the behavioral and structural rt-level are classified. The principles of the TUD Symbolic Simulator used for equivalence checking are briefly outlined. The application of the tool to property checking is demonstrated. Experimental results with input languages Esterel and C are given.