Automatic formal verification of DSP software

Authors:
David W. Currie;Alan J. Hu;Sreeranga Rajan
Affiliations:
University of British Columbia, Mentor Graphics, Billerica, MA;Dept. of Computer Science, University of British Columbia, Vancouver, BC, Canada;Fujitsu Laboratories of America, Sunnyvale, CA
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

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Abstract

This paper describes a novel formal verification approach for equivalence checking of small, assembly-language routines for digital signal processors (DSP). By combining control-flow analysis, symbolic simulation, automatic decision procedures, and some domain-specific optimizations, we have built an automatic verification tool that compares structurally similar DSP assembly language routines. We tested our tool on code samples taken from a real application program and discovered several previously unknown bugs automatically. Runtime and memory requirements were reasonable on all examples. Our approach should generalize easily for multiple DSP architectures, eventually allowing comparison of code for two different DSPs (e.g., to verify a port from one DSP to another) and handling more complex DSPs (e.g. statically-scheduled, VLIW).