Automatic formal verification of DSP software
Proceedings of the 37th Annual Design Automation Conference
Cutpoints for formal equivalence verification of embedded software
Proceedings of the 5th ACM international conference on Embedded software
Embedded software verification using symbolic execution and uninterpreted functions
International Journal of Parallel Programming
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A method for the verification of embedded software correctness is presented. A formal model for an actual commercial microprocessor is established. This is done by modeling the instruction set and processor architecture. Embedded software takes the form of the assembly program code to be run on the processor. Specifications are given as CTL temporal logic formulae. The method has been implemented in the SMV model checker and is illustrated by a practical embedded system application: a mouse controller. The inconsistency of the specification and the implementation as an assembly language program as it has been published in the applications book of the manufacturer has been uncovered.