Computer
Verification of SpecC using predicate abstraction
Formal Methods in System Design
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
VCC: A Practical System for Verifying Concurrent C
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
seL4: formal verification of an OS kernel
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
On the Design of Flexible Real-Time Schedulers for Embedded Systems
CSE '09 Proceedings of the 2009 International Conference on Computational Science and Engineering - Volume 02
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Isabelle/HOL: a proof assistant for higher-order logic
Isabelle/HOL: a proof assistant for higher-order logic
Scoot: a tool for the analysis of SystemC models
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Modular verification of preemptive OS kernels
Proceedings of the 16th ACM SIGPLAN international conference on Functional programming
Local verification of global invariants in concurrent programs
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Implementing OS components in hardware using AOP
ACM SIGOPS Operating Systems Review
Bounded model checking of high-integrity software
Proceedings of the 2013 ACM SIGAda annual conference on High integrity language technology
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The increasing complexity of embedded systems is pushing their design to System-Level, thus leading to a convergence between software and hardware. Consequently, operating systems in this realm are also being required to deliver their services both as software and as hardware. In such a scenario, it is desirable to verify system properties regardless of whether its components are instantiated at software or hardware. In this paper, we describe an approach to formally verify functional correctness and safety properties of such system-level component. The approach is illustrated by a case study of EPOS' scheduler, whose implementation can be driven to yield both a software instance compiled by the GCC C++ compiler or a hardware instance synthesized by the CatapultC ESL tool. We demonstrate that the scheduler follows its specification regardless of the domain for which it is instantiated. We also demonstrate that the proposed approach causes no run-time overhead, since the adopted Software Model Checking techniques are deployed at compile-time.