Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Predicate Abstraction of ANSI-C Programs Using SAT
Formal Methods in System Design
Word level predicate abstraction and refinement for verifying RTL verilog
Proceedings of the 42nd annual Design Automation Conference
Hybrid CEGAR: combining variable hiding and predicate abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analyzing k-step induction to compute invariants for SAT-based property checking
Proceedings of the 47th Design Automation Conference
An automatic method for the dynamic construction of abstractions of states of a formal model
Cybernetics and Systems Analysis
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As first step, most model checkers used in the hardware industry convert a high-level register transfer language (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels, and thus, are less scalable. The RTL level of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. We describe a hardware model checking tool, VCEGAR, which performs verification at the RTL level using software verification techniques. It implements predicate abstraction and a refinement loop as used in software verification. The novel aspects are the generation of new word-level predicates, an efficient predicate image computation in presence of a large number of predicates, and precise modeling of the bit-vector semantics of hardware designs.