A practical algorithm for exact array dependence analysis
Communications of the ACM
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
On the Limitations of Ordered Representations of Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Symmetry Reductions inModel Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Coverage-directed validation of hardware models
Coverage-directed validation of hardware models
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Reducing run times and the amount of memory needed for computations is one requirement in order to match today's sizes of real world designs in formal hardware verification. Designs are usually given as Register-Transfer-Level (RTL) specifications, but most of today's hardware verification tools are based on bit-level methods. However, designs, like for example ALUs or bus interfaces, often have very regular structures that can be described easily on a higher level of abstraction. This information is lost on bit-level and thus cannot be utilized by verification tools, if verification procedures operate on the basis of bit-level descriptions. Recently, several approaches to formal circuit verification have been proposed that make use of such regularities. These approaches are based on word-level descriptions as they are available on the RTL. We introduce the main concepts of formal verification on the RTL and give a brief overview of existing techniques. Recent developments are outlined, and based on real world examples we show the advantages of the use of word-level information for equivalence checking and property checking.