Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking of datapaths based on canonical arithmetic expressions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Verifying systems with integer constraints and Boolean predicates: a composite approach
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Polynomial methods for component matching and verification
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Polynomial methods for allocating complex components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Computational Logic (TOCL)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Advanced Engineering Mathematics: Maple Computer Guide
Advanced Engineering Mathematics: Maple Computer Guide
Polynomial Algorithms in Computer Algebra
Polynomial Algorithms in Computer Algebra
The K*BMD: A Verification Data Structure
IEEE Design & Test
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CVC: A Cooperating Validity Checker
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
An infrastructure for rtl validation and verification
An infrastructure for rtl validation and verification
Algorithms for Taylor Expansion Diagrams
ISMVL '04 Proceedings of the 34th International Symposium on Multiple-Valued Logic
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Efficient factorization of DSP transforms using taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Variable ordering for taylor expansion diagrams
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data-flow transformations using Taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe
SPaC: a symbolic pareto calculator
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Integration, the VLSI Journal
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing data flow graphs to minimize hardware implementation
Proceedings of the Conference on Design, Automation and Test in Europe
Sal/Svm: an assembly language and virtual machine for computing with non-enumerated sets
Virtual Machines and Intermediate Languages
Algebraic approach to arithmetic design verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Accelerating an application domain with specialized functional units
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 14.98 |
A Taylor Expansion Diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated.