Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
IEEE Transactions on Computers
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Decision Procedures: An Algorithmic Point of View
Decision Procedures: An Algorithmic Point of View
An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper describes an algebraic approach to functional verification of arithmetic circuits specified at bit level. The circuit is represented as a network of half adders, full adders, and inverters, and modeled as a system of linear equations. The proof of functional correctness of the design is obtained by computing its algebraic signature using standard LP solver and comparing it with the reference signature provided by the designer. Initial experimental results and comparison with SMT solvers show that the method is efficient, scalable and applicable to large arithmetic designs, such as multipliers.