Mathematical framework for representing discrete functions as word-level polynomials

Authors:
D. K. Pradhan;S. Askar;M. Ciesielski
Affiliations:
Dept. of Comput. Sci., Bristol Univ., UK;Inst. of Comput. Sci., Bremen Univ., Germany;Dipt. di Inf., Verona Univ., Italy
Venue:
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Year:
2003

Citing 16
Cited 5

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Efficient implementation of a BDD package

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Spectral transforms for large boolean functions with applications to technology mapping

DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams

DAC '94 Proceedings of the 31st annual Design Automation Conference
Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
FGILP: an integer linear program solver based on function graphs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Polynomial methods for component matching and verification

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Formal verification of word-level specifications

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Polynomial methods for allocating complex components

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Using symbolic algebra in algorithmic level DSP synthesis

Proceedings of the 38th annual Design Automation Conference
The Design and Analysis of Computer Algorithms

The Design and Analysis of Computer Algorithms
The K*BMD: A Verification Data Structure

IEEE Design & Test
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

Proceedings of the conference on Design, automation and test in Europe
High-level design verification using Taylor Expansion Diagrams: first results

HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
A Theory of Galois Switching Functions

IEEE Transactions on Computers

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

IEEE Transactions on Computers
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields

IEEE Transactions on Computers
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

IEEE Transactions on Computers
Optimization of polynomial datapaths using finite ring algebra

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.01

Visualization

Abstract

This paper presents a mathematical framework for modeling arithmetic operators and other RTL design modules as discrete word-level functions and proposes a polynomial representation of those functions. The proposed representation attempts to bridge the gap between bit-level BDD representations and word-level representations, such as *BMDs and TEDs.