Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

Authors:
M. Ciesielski;P. Kalla;Z. Zeng;B. Rouzeyre
Affiliations:
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst;Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, France
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

This paper presents a new, compact, canonicalgraph-based representation, called Taylor Expansion Diagrams(TEDs). It is based on a general non-binary decompositionprinciple using Taylor series expansion. It can be exploitedto facilitate the verification of high-level (RTL) designdescriptions. We present the theory behind TEDs, commentupon its canonicity property and demonstrate that the representationhas linear space complexity. Its application to equivalencechecking of high-level design descriptions is discussed.