Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Residue BDD and its application to the verification of arithmetic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verifying imprecisely working arithmetic circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On feasible multivariate polynomial interpolations over arbitrary fields
ISSAC '99 Proceedings of the 1999 international symposium on Symbolic and algebraic computation
Polynomial circuit models for component matching in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Symbolic algebra and timing driven data-flow synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We address verification of imprecise datapath circuits with sequential elements. Using Arithmetic Transform (AT) and its extensions, we verify the sequential datapath circuits with finite precision. An efficient formulation of the precision verification is presented as a polynomial maximization search over Boolean inputs. Using a branch-and-bound search for the precision error and the block-level composition of ATs, we verify the approximated, rounded and truncated pipelined datapaths.