Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
The good, the bad, and the ugly of silicon debug
Proceedings of the 43rd annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Reap what you sow: spare cells for post-silicon metal fix
Proceedings of the 2008 international symposium on Physical design
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validation is the use of spare cells. In the literature, most existing works focus on developing new delicate spare cell structures. On the other hand, the placement of spare cells has a crucial impact on the design cycle and cost of the post-silicon debugging; however, there exists not much work on this placement problem. In this paper, we propose the first spare-cell-aware analytical placement framework which predicts the spare cell requirement and considers spare cell insertion during global placement. We also propose a multilevel spare cell insertion technique which provides a more efficient spare cell planning and a better control of quality impact due to spare cell insertion. To guide the selection of available spare cell positions during insertion, we propose a mixed-integer-linear-programming formulation to determine the optimal spare cell positions. Experimental results show that our algorithm can averagely achieve 17--33% and 1.77--2.61X better quality of spare cell insertion than that of the existing spare cell insertion algorithms, UniSpare [10] and PostSpare [22, 26], on the tested real designs with 1--5% spare cell insertion rates.