Applied multivariate statistical analysis
Applied multivariate statistical analysis
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Refined statistical static timing analysis through
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
Confidence scalable post-silicon statistical delay prediction under process variations
Proceedings of the 44th annual Design Automation Conference
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis and optimization has become essential. While statistical timing analysis has an important role to play in this process, it is equally important to develop die-specific delay prediction techniques using postsilicon measurements. We present a novel method for postsilicon delay analysis. We gather data from a small number of on-chip test structures, and combine this information with presilicon statistical timing analysis to obtain narrow die-specific timing probability density function (PDF). Experimental results show that for the benchmark suite being considered, taking all parameter variations into consideration, our approach can obtain a PDF whose standard deviation is 79.0% smaller, on average, than the statistical timing analysis result. The accuracy of the method defined by our metric is 99.6% compared to Monte Carlo simulation. The approach is scalable to smaller test structure overheads and can still produce acceptable results.