Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
Information Theory, Inference & Learning Algorithms
Information Theory, Inference & Learning Algorithms
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
A framework for accounting for process model uncertainty in statistical static timing analysis
Proceedings of the 44th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
A framework for scalable postsilicon statistical delay prediction under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DIGMAP-detector: an intelligent computerized tool to detect and predict digital map pattern
ACE'10 Proceedings of the 9th WSEAS international conference on Applications of computer engineering
Introducing an intelligent computerized tool to detect and predict urban growth pattern
WSEAS Transactions on Computers
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Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits.