Applied multivariate statistical analysis
Applied multivariate statistical analysis
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for scalable postsilicon statistical delay prediction under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Proceedings of the 2009 International Conference on Computer-Aided Design
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust spatial correlation extraction with limited sample via L1-norm penalty
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that gathers data from a small number of on-chip test structures, and combines this information with pre-silicon statistical timing analysis to obtain narrow, die-specific, timing PDFs. Experimental results show that for the benchmark suite being considered, taking all parameter variations into consideration, our approach can get a PDF with the standard deviation 83.5% smaller on average than the SSTA result. The approach is scalable to smaller test structure overheads.